In this paper, we study the complex multiphysics interactions between performance, energy and temperature. The price paid however is, tight thermal constraints. 3D stacking of memory and logic dies delivers an order of magnitude improvement in available memory bandwidth.
The consistent demand for better performance has lead to innovations at hardware and microarchitectural levels. Experimental results show the new method outperforms the linear model predictive control based method in temperature management quality with negligible computing overhead. By approximating the nonlinearity accurately with the PWL thermal model and being equipped with predictive control technique, the new DTM can achieve an overall high quality temperature management with smooth and accurate temperature tracking. Based on the PWL thermal model, a new predictive control method is proposed to compute the future power recommendation for DTM. These Taylor expansion points are carefully selected by a systematic scheme which exploits the thermal behavior property of the IC chips. First, a PWL thermal model is built by combining multiple local linear thermal models expanded at several Taylor expansion points. In this paper, a new dynamic thermal management (DTM) method with piecewise linear (PWL) thermal model based predictive control is proposed to solve the nonlinear control problem. This is because the leakage power, which is significant in today's chips, is nonlinearly related to temperature, resulting in a complex nonlinear control problem in thermal management. Performing thermal management on new generation IC chips is challenging. Our approach leads to a significant reliability improvement (around 20%) over baseline DVFS techniques. Also, task reassignment across cores is driven by estimates of current core reliability, which is superior to the usual approach of simply using either current temperature or temperature history.
That is, by preferentially slowing down high-activity task phases, significant additional savings in energy and thermal stress can be attained for a given amount of computational slowdown this approach is shown to be superior to conventional methods that use DVFS without regard to activity levels. This paper describes a novel approach to reduce thermally-induced damage in CPS processors by targeting Dynamic Voltage and Frequency Scaling (DVFS) to high-activity task phases. This in turn can require provisioning of significant amounts of additional computational hardware to withstand more frequent failures, with obvious implications for sustainability. High operating temperatures can dramatically shorten processor life. Thermal stress is often a major concern for processors embedded in such systems. Cyber-Physical Systems (CPS) are increasingly used in a variety of transportation, healthcare, electricity grid, and other applications.
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